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features ? single 2.5v or 2.7v to 3.6v supply ? rapids tm serial interface: 66mhz maximum clock frequency ? spi compatible modes 0 and 3 ? user configurable page size ? 256-bytes per page ? 264-bytes per page ? page size can be factory pre-configured for 256-bytes ? page program operation ? intelligent programming operation ? 2,048 pages (256-/264-bytes/page) main memory ? flexible erase options ? page erase (256-bytes) ? block erase (2-kbytes) ? sector erase (64-kbytes) ? chip erase (4mbits) ? two sram data buffers (256-, 264-bytes) ? allows receiving of data while reprogramming the flash array ? continuous read capability through entire array ? ideal for code shadowing applications ? low-power dissipation ? 7ma active read current typical ?25 a standby current typical ?15 a deep power-down typical ? hardware and software data protection features ? individual sector ? sector lockdown for secure code and data storage ? individual sector ? security: 128-byte security register ? 64-byte user programmable space ? unique 64-byte device identifier ? jedec standard manufacturer and device id read ? 100,000 program/erase cycles per page minimum ? data retention ? 20 years ? industrial temperature range ? green (pb/halide-free/rohs compliant) packaging options 1. description the AT45DB041D is a 2.5v or 2.7v, serial-interface flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. the AT45DB041D supports rapids serial interface for applications requiring very high speed operations. rapids serial interface is spi compatible for frequencies up to 66mhz. its 4,325,376-bits of memory are organized as 2,048 pages of 256-bytes or 264-bytes each. in addition to the main memory, the AT45DB041D also contains two sram buffers of 256-/264-bytes each. the buffers allow the receiving of data while a page in the main memory is being reprogrammed, as well as writing a continuous data stream. eeprom emulation (bit or byte alterability) is easily handled with a self-con- tained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel interface, the dataflash uses a rapids serial interface to sequentially access its data. the simple sequential access dramatically 4-megabit 2.5-volt or 2.7-volt dataflash ? AT45DB041D (not recommended for new designs. use at45db041e.) 3595t?dflash?8/2013
2 3595t?dflash?8/2013 AT45DB041D reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. the device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential. to allow for simple in-system reprogrammability, the AT45DB041D does not require high input voltages for programming. the device operates from a single power supply, 2.5v to 3.6v or 2.7v to 3.6v, for both the program and read operations. the AT45DB041D is enabled through the chip select pin ( c s) and accessed via a three-wire interfac e consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming and erase cycles are self-timed. 2. pin configurations and pinouts table 2-1. pin configurations symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in the standby mode (not deep power-down mode), and the output pin (so) will be in a high-impedance state. when the device is deselected, data will not be accepted on the input pin (si). a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. ? input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. ? input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. ? output wp write protect: when the wp pin is asserted, all sectors specified for protection by the sector protection register will be protected against program and erase operations regardless of whether the enable sector protection command has been issued or not. the wp pin functions independently of the software controlled protection method. after the wp pin goes low, the content of the sector protection register cannot be modified. if a program or erase command is issued to the device while the wp pin is asserted, the device will simply ignore the command and perform no operation. the device will return to the idle state once the cs pin has been deasserted. the enable sector protection command and sector lockdown command, however, will be recognized by the device when the wp pin is asserted. the wp pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input reset reset: a low state on the reset pin ( reset) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature are not utilized it is recommended that the reset pin be driven high externally. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? ground
3 3595t?dflash?8/2013 AT45DB041D note: 1. the metal pad on the bottom of the mlf package is floating. this pad can be a ?no connect? or connected to gnd 3. block diagram figure 2-1. mlf (vdfn)top view figure 2-2. soic top view si sck reset cs so gnd vcc wp 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5 si sck reset cs so gnd vcc wp flash memory array page (256-/264-bytes) buffer 2 (256-/264-bytes) buffer 1 (256-/264-bytes) i/o interface sck cs reset vcc gnd wp so si
4 3595t?dflash?8/2013 AT45DB041D 4. memory array to provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of granularity comprising of sectors, blocks, and pages. the ?memory architecture diagram? illus- trates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page-by-page basis. the erase operations can be performed at the chip, sector, block or page level. figure 4-1. memory architecture diagram 5. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in tables 15-1 through 15-7 . a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the c s pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instruct ions, addresses, and data are tr ansferred with the most significant bit (msb) first. buffer addressing for the dataflash standard page size (264-bytes) is referenced in the data- sheet using the terminology bea8 - bfa0 to denote the nine address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology pa10 - pa0 and ba8 - ba0, where pa10 - pa0 denotes the 11 address bits required to desig- nate a page address and ba8 - ba0 denotes the nine address bits required to designate a byte address within the page. for the ?power of 2? binary page size (256-bytes), the buffer addressing is referenced in the datasheet using the conventional terminology bfa7 - bfa0 to denote the eight address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology a18 - a0, where a18 - a8 denotes the 11 address bits required to desig- nate a page address and a7 - a0 denotes the eight address bits required to designate a byte address within a page. sector 0a = 8 pages 2,048 / 2,112-bytes sector 0b = 248 pages 63,488 / 65,472-bytes block = 2,048 / 2,112-bytes 8 pages sector 0a sector 0b page = 256 / 264-bytes page 0 page 1 page 6 page 7 page 8 page 9 page 2,046 page 2,047 block 0 page 14 page 15 page 16 page 17 page 18 block 1 sector architecture block architecture page architecture block 0 block 1 block 30 block 31 block 32 block 33 block 254 block 255 block 62 block 63 block 64 block 65 sector 1 sector 7 = 256 pages 65,536 / 67,584-bytes block 2 sector 1 = 256 pages 65,536 / 67,584-bytes sector 6 = 256 pages 65,536 / 67,584-bytes sector 2 = 256 pages 65,536 / 67,584-bytes
5 3595t?dflash?8/2013 AT45DB041D 6. read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two sram data buffers. the dataflash supports rapids protocols for mode 0 and mode 3. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. 6.1 continuous array read (legacy command ? e8h): up to 66mhz by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional ad dressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. to perform a continuous read from the dataflash standard page size (264-bytes), an opcode of e8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four don?t care bytes. the first 11 bits (pa10 - pa0) of the 20-bit address sequence specify which page of the main memory array to read, and the last nine bits (ba8 - ba0) of the 20-bit address sequence specify the starting byte address within the page. to perform a continuous read from the binary page size (256-bytes), the opcode (e8h) must be clocked into the device followed by three address bytes and four don?t care bytes. the first 11 bits (a18 - a8) of the 19-bits sequence specify which page of the main memory array to read, and the last 8 bits (a7 - a0) of the 19-bits address sequence specify the starting byte address within the page. the don?t care bytes that follow the address bytes are needed to initialize the read op eration. following the don?t care bytes, addi- tional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the la st bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with cross- ing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the c s pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.2 continuous array read (high frequency mode ? 0bh): up to 66mhz this command can be used with the serial interface to read the main memory array sequentially in high speed mode for any clock frequency up to the maximum specified by f car1 . to perform a continuous read array with the page size set to 264-bytes, the cs must first be asserted then an opcode 0bh must be clocked into the device followed by three address bytes and a dummy byte. the first 11 bits (pa10 - pa0) of the 20-bit address sequence specify which page of the main memory array to read, and the last nine bits (ba8 - ba0) of the 20-bit address sequence specify the starting byte address within the page. to perform a continuous read with the page size set to 256-bytes, the opcode, 0bh, must be clocked into the device followed by three address bytes (a18 - a0) and a dummy byte. following the dummy byte, additional clock pulses on the sck pin will result in data being output on the so (serial output) pin.
6 3595t?dflash?8/2013 AT45DB041D the cs pin must remain low during the loading of the opcode, the address bytes, and the read- ing of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will con- tinue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.3 continuous array read (low frequency mode: 03h): up to 33mhz this command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to maximum frequencies specified by f car2 . to perform a continuous read array with the page size set to 264-bytes, the c s must first be asserted then an opcode, 03h, must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). the first 11 bits (pa10 - pa0) of the 20-bit address sequence specify which page of the main memory array to read, and the last nine bits (ba8 - ba0) of the 20-bit address sequence specify the starting byte address within the page. to perform a contin- uous read with the page size set to 256-bytes, the opcode, 03h, must be clocked into the device followed by three address bytes (a18 - a0). following the address bytes, additional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, and the read- ing of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will con- tinue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.4 main memory page read a main memory page read allows the user to read data directly from any one of the 2,048 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read from the dataflash standard page size (264-bytes), an opcode of d2h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four don?t care bytes. the first 11 bits (pa10 - pa0) of the 20-bit address sequence specify the page in main memory to be read, and the last nine bits (ba8 - ba0) of the 20-bit address sequence specify the starting byte address within that page. to start a page read from the binary page size (256-bytes), the opcode d2h must be clocked into the device followed by three address bytes and four don?t care bytes. the first 11 bits (a18 - a8) of the 19-bits sequence specify which page of the main memory array to read, and the last 8 bits (a7 - a0) of the 19-bits address sequence specify the starting byte address within the page. the don?t care bytes that follow the address bytes are sent to initialize the read operation. following the don?t care bytes, additional pulses on sck result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main
7 3595t?dflash?8/2013 AT45DB041D memory is reached, the device will continue reading back at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.5 buffer read the sram data buffers can be accessed independently from the main memory array, and utiliz- ing the buffer read command allows data to be sequentially read directly from the buffers. four opcodes, d4h or d1h for buffer 1 and d6h or d3h for buffer 2 can be used for the buffer read command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the buffer. the d4h and d6h opcode can be used at any sck frequency up to the maximum specified by f car1 . the d1h and d3h opcode can be used for lower frequency read operations up to the maximum specified by f car2 . to perform a buffer read from the dataflash standard buffer (264-bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 don?t care bits and nine buffer address bits (bfa8 - bfa0). to perform a buffer read from the binary buffer (256- bytes), the opcode must be clocked into the de vice followed by three address bytes comprised of 16 don?t care bits and 8 buffer address bits (bfa7 - bfa0). following the address bytes, one don?t care byte must be clocked in to initialize the read operation. the c s pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). 7. program and erase commands 7.1 buffer write data can be clocked in from the input pin (si) into either buffer 1 or buffer 2. to load data into the dataflash standard buffer (264-bytes), a 1-byte opcode, 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 15 don?t care bits and nine buffer address bits (bfa8 - bfa0). the nine buffer address bits specify the first byte in the buffer to be written. to load data into th e binary buffers (256-bytes each), a 1-byte opcode 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 16 don?t care bits and 8 buffer address bits (bfa7 - bfa0). the eight buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin.
8 3595t?dflash?8/2013 AT45DB041D 7.2 buffer to main memory page program with built-in erase data written into either buffer 1 or buffer 2 can be programmed into the main memory. a 1-byte opcode, 83h for buffer 1 or 86h for buffer 2, must be clocked into the device. for the dataflash standard page size (264-bytes), the opcode must be followed by three address bytes consist of four don?t care bits, 11 page address bits (pa10 - pa0) that specify the page in the main memory to be written and nine don?t care bits. to perform a buffer to main memory page program with built-in erase for the binary page size (256-bytes), the opcode 83h for buffer 1 or 86h for buffer 2, must be clocked into the device followed by three address bytes consisting of five don?t care bits 11 page address bits (a18 - a8) that specify the page in the main memory to be written and eight don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. both the erase and the program- ming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. 7.3 buffer to main memory page program without built-in erase a previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. a 1-byte opcode, 88h for buffer 1 or 89h for buffer 2, must be clocked into the device. for the dataflash standard page size (264-bytes), the opcode must be followed by three address bytes consist of four don?t care bits, 11 page address bits (pa10 - pa0) that spec- ify the page in the main memory to be written and nine don?t care bits. to perform a buffer to main memory page program without built-in erase for the binary page size (256-bytes), the opcode 88h for buffer 1 or 89h for buffer 2, must be clocked into the device followed by three address bytes consisting of five don?t care bits, 11 page address bits (a18 - a8) that specify the page in the main memory to be written and eight don?t care bits . when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (page erase or block erase). the programming of the page is internally self-timed and should take place in a maximum time of t p . during this time, the status register will indicate that the part is busy. 7.4 page erase the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program to be utilized at a later time. to perform a page erase in the dataflash standard page size (264-bytes), an opcode of 81h must be loaded into the device, followed by three address bytes comprised of four don?t care bits, 11 page address bits (pa10 - pa0) that specify the page in the main memory to be erased and nine don?t care bits. to perform a page erase in the binary page size (256-bytes), the opcode 81h must be loaded into the device, followed by three address by tes consist of five don?t care bits, 11 page address bits (a18 - a8) that specify the page in the main memory to be erased and eight don?t care bits. when a low-to-high transition occurs on the c s pin, the part will erase the selected page (the erased state is a logical 1). the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the status register will indicate that the part is busy.
9 3595t?dflash?8/2013 AT45DB041D 7.5 block erase a block of eight pages can be erased at one time. this command is useful when large amounts of data has to be written into the device. this will avoid using multiple page erase commands. to perform a block erase for the dataflash standa rd page size (264-bytes), an opcode of 50h must be loaded into the device, followed by three address bytes comprised of four don?t care bits, eight page address bits (pa10 - pa3) and 12 don?t care bits. the eight page address bits are used to specify which block of eight pages is to be erased. to perform a block erase for the binary page size (256-bytes), the opcode 50h must be loaded into the device, followed by three address bytes consisting of five don?t care bits, eight page address bits (a18 - a11) and 11 don?t care bits. the nine page address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the c s pin, the part will erase the selected block of eight pages. the erase operation is internally self-timed and should take place in a max- imum time of t be . during this time, the status register will indicate that the part is busy. table 7-1. block erase addressing pa10/ a18 pa9/ a17 pa8/ a16 pa7/ a15 pa6/ a14 pa5/ a13 pa4/ a12 pa3/ a11 pa2/ a10 pa1/ a9 pa0/ a8 block 00000000xxx 0 00000001xxx 1 00000010xxx 2 00000011xxx 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11111100xxx 252 11111101xxx 253 11111110xxx 254 11111111xxx 255
10 3595t?dflash?8/2013 AT45DB041D 7.6 sector erase the sector erase command can be used to individually erase an y sector in the main memory. there are eight sectors and only one sector can be erased at one time. to perform sector 0a or sector 0b erase for the dataflash standard page size (264-bytes), an opcode of 7ch must be loaded into the device, followed by three address bytes comprised of 4 don?t care bits, 8 page address bits (pa10 - pa3) and 12 don?t care bits. to perform a sector 1-7 erase, the opcode 7ch must be loaded into the device, followed by three address bytes comprised of four don?t care bits, three page address bits (pa10 - pa8) and 17 don?t care bits. to perform sector 0a or sector 0b erase for the binary page size (256-bytes), an opcode of 7ch must be loaded into the device, followed by three address bytes comprised of five don?t care bit and eight page address bits (a18 - a11) and 11 don?t care bits. to perform a sector 1-15 erase, the opcode 7ch must be loaded into the device, followed by three address bytes comprised of five don?t care bit and three page address bits (a18 - a16) and 16 don?t care bits. the page address bits are used to specify any valid address location within the sector which is to be erased. when a low-to-high transition occurs on the c s pin, the part will erase the selected sector. the erase operation is internally self-timed and should take place in a maximum time of t se . during this time, the status register will indicate that the part is busy. 7.7 chip erase (1) the entire main memory can be erased at one time by using the chip erase command. to execute the chip erase command, a 4-byte command sequence c7h, 94h, 80h and 9ah must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. after the last bit of the opcode sequence has been clocked in, the cs pin can be deas- serted to start the erase process. the erase operation is internally self-timed and should take place in a time of t ce . during this time, the status register will indicate that the device is busy. the chip erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. only those sectors that are not protected or locked down will be erased. table 7-2. sector erase addressing pa10/ a18 pa9/ a17 pa8/ a16 pa7/ a15 pa6/ a14 pa5/ a13 pa4/ a12 pa3/ a11 pa2/ a10 pa1/ a9 pa0/ a8 sector 00000000xxx 0a 00000001xxx 0b 0 0 1xxxxxxxx 1 0 1 0xxxxxxxx 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0xxxxxxxx 4 1 0 1xxxxxxxx 5 1 1 0xxxxxxxx 6 1 1 1xxxxxxxx 7
11 3595t?dflash?8/2013 AT45DB041D the wp pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. table 7-3. chip erase command figure 7-1. chip erase note: 1. refer to the errata regarding chip erase on page 52 7.8 main memory page program through buffer this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first clocked into buffer 1 or buffer 2 from the input pin (si) and then programmed into a specified page in the main memory. to perform a main memory page program through buffer for the dataflash standard page size (264-bytes), a 1-byte opcode, 82h for buffer 1 or 85h for buffer 2, must first be clocked into the device, followed by three address bytes. the address bytes are comprised of four don?t care bits, 11 page address bits, (pa10 - pa0) that select the page in the main memory where data is to be written, and nine buffer address bits (bfa8 - bfa0) that select the first byte in the buffer to be written. to perform a main memory page program through buffer for the binary page size (256-bytes), the opcode 82h for buffer 1 or 85h for buffer 2, must be clocked into the device followed by three address bytes consisting of five don?t care bits, 11 page address bits (a18 - a8) that specify the page in the main memory to be written, and eight buffer address bits (bfa7 - bfa0) that selects the first byte in the buffer to be written. after all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transi- tion on the c s pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. both the erase and the program- ming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. 8. sector protection two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. the software controlled method relies on the use of software commands to enable and disable sector protection while the hardware con- trolled method employs the use of the write protect ( w p) pin. the selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the nonvolatile sector protection register. the status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the status register. command byte 1 byte 2 byte 3 byte 4 chip erase c7h 94h 80h 9ah opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
12 3595t?dflash?8/2013 AT45DB041D 8.1 software sector protection 8.1.1 enable sector protection command sectors specified for protection in the sector protection register can be protected from program and erase operations by issuin g the enable sector protection command. to enable the sector protection using the software controlled method, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (si). after the last bit of the command sequence has been clocked in, the c s pin must be deasserted after which the sector protection will be enabled. table 8-1. enable sector protection command figure 8-1. enable sector protection 8.1.2 disable sector protection command to disable the sector protection using the software controlled method, the c s pin must first be asserted as it would be with any other command. once the c s pin has been asserted, the appropriate 4-byte sequence for the disable sector protection command must be clocked in via the input pin (si). after the last bit of the command sequence has been clocked in, the c s pin must be deasserted after which the sector protection will be disabled. the wp pin must be in the deasserted state; otherwise, the disable sector protection command will be ignored. table 8-2. disenable sector protection command figure 8-2. disable sector protection 8.1.3 various aspects about software controlled protection software controlled protection is us eful in applications in which the w p pin is not or cannot be controlled by a host processor. in such instances, the wp pin may be left floating (the wp pin is internally pulled high) and sector protection can be controlled using the enable sector protection and disable sector protection commands. command byte 1 byte 2 byte 3 byte 4 enable sector protection 3dh 2ah 7fh a9h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si command byte 1 byte 2 byte 3 byte 4 disable sector protection 3dh 2ah 7fh 9ah opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
13 3595t?dflash?8/2013 AT45DB041D if the device is power cycled, then the software controlled protection will be disabled. once the device is powered up, the enable sector protection command should be reissued if sector pro- tection is desired and if the wp pin is not used. 9. hardware controlled protection sectors specified for protection in the sector protection register and the sector protection reg- ister itself can be protected from program and erase operations by asserting the w p pin and keeping the pin in its asserted state. the sector protection register and any sector specified for protection cannot be erased or reprogrammed as long as the w p pin is asserted. in order to modify the sector protection register, the w p pin must be deasserted. if the w p pin is perma- nently connected to gnd, then the content of the sector protection register cannot be changed. if the w p pin is deasserted, or permanently connected to v cc , then the content of the sector protection register can be modified. the w p pin will override the software controlled protection method but only for protecting the sectors. for example, if the sectors were not previously protected by the enable sector protec- tion command, then simply asserting the w p pin would enable the sector protection within the maximum specified t wpe time. when the w p pin is deasserted; however, the sector protection would no longer be enabled (after the maximum specified t wpd time) as long as the enable sec- tor protection command was not issued while the w p pin was asserted. if the enable sector protection command was issued before or while the wp pin was asserted, then simply deassert- ing the w p pin would not disable the sector protection. in this case, the disable sector protection command would need to be issued while the wp pin is deasserted to disable the sec- tor protection. the disable sector protection command is also ignored whenever the w p pin is asserted. a noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the wp pin. the table below details the sector protection status for various scenarios of the w p pin, the enable sector protection command, and the disable sector protection command. figure 9-1. wp pin and protection status wp 12 3 table 9-1. wp pin and protection status time period wp pin enable sector protection command disable sector protection command sector protection status sector protection register 1 high command not issued previously ? issue command x issue command ? disabled disabled enabled read/write read/write read/write 2 low x x enabled read only 3 high command issued during period 1 or 2 ? issue command not issued yet issue command ? enabled disabled enabled read/write read/write read/write
14 3595t?dflash?8/2013 AT45DB041D 9.1 sector protection register the nonvolatile sector protection register specifies which sectors are to be protected or unpro- tected with either the software or hardware controlled protection methods. the sector protection register contains eight bytes of data, of which byte locations zero through seven contain values that specify whether sectors zero through seven will be protected or unprotected. the sector protection register is user modifiable and must first be erased before it can be reprogrammed. table 9-3 illustrates the format of the sector protection register.: note: 1. the default value for bytes 0 through 7 when shipped from adesto is 00h x = don?t care 9.1.1 erase sector protection register command in order to modify and change the values of the sector protection register, it must first be erased using the erase sector protection register command. to erase the sector protection register, the c s pin must first be asserted as it would be with any other command. once the c s pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the si pin. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and cfh. after the last bit of the opcode sequence has been clocked in, the c s pin must be deasserted to initiate the internally self-timed erase cycle. the erasing of the sector protection register should take place in a time of t pe , during which time the status register will indicate that the device is busy. if the device is powered- down before the completion of the erase cycle, then the contents of the sector protection regis- ter cannot be guaranteed. the sector protection register can be erased with the sector protection enabled or disabled. since the erased state (ffh) of each byte in the sector protection register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. if for some reason an erroneous program or erase com- mand is sent to the device immediately after erasing the sector protection register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. table 9-2. sector protection register sector number 0 (0a, 0b) 1 to 7 protected see table 9-3 ffh unprotected 00h table 9-3. sector 0 (0a, 0b) 0a 0b bit 3, 2 data value (page 0-7) (page 8-255) bit 7, 6 bit 5, 4 bit 1, 0 sectors 0a, 0b unprotected 00 00 xx xx 0xh protect sector 0a 11 00 xx xx cxh protect sector 0b (page 8-255) 00 11 xx xx 3xh protect sectors 0a (page 0-7), 0b (page 8-255) (1) 11 11 xx xx fxh
15 3595t?dflash?8/2013 AT45DB041D table 9-4. erase sector protection figure 9-2. erase sector protection register 9.1.2 program sector protection register command once the sector protection register has been erased, it can be reprogrammed using the program sector protection register command. to program the sector protection register, the c s pin must first be asserted and the appropri- ate 4-byte opcode sequence must be clocked into the device via the si pin. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and fch. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the sector pro- tection register must be clocked in. as described in section 9.1 , the sector protection register contains 8-bytes of data, so 8 bytes must be clocked into the device. the first byte of data corre- sponds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data corresponding to sector 7. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the inter- nally self-timed program cycle. the programming of the sector protection register should take place in a time of t p , during which time the status register will indicate that the device is busy. if the device is powered-down during the program cycle, then the contents of the sector protection register cannot be guaranteed. if the proper number of data bytes is not clocked in before the c s pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed. for example, if only the first two bytes are clocke d in instead of the complete 8-bytes, then the protection status of the last six sectors cannot be guaranteed. furthermore, if more than 8-bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for instance, if 9-bytes of data are clocked in, then the 9 th byte will be stored at byte location zero of the sector protection register. if a value other than 00h or ffh is clocked into a byte location of the sector protection register, then the protection status of the sector corresponding to that byte location cannot be guaran- teed. for example, if a value of 17h is clocked into byte location two of the sector protection register, then the protection status of sector two cannot be guaranteed. the sector protection register can be reprogrammed while the sector protection enabled or dis- abled. being able to reprogram the sector protection register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than disabling sector protection completely. the program sector protection register command utilizes the internal sram buffer 1 for processing. therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. command byte 1 byte 2 byte 3 byte 4 erase sector protection register 3dh 2ah 7fh cfh opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
16 3595t?dflash?8/2013 AT45DB041D table 9-5. program sector protection register command figure 9-3. program sector protection register 9.1.3 read sector protection register command to read the sector protection register, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of 32h and three dummy bytes must be clocked in via the si pin. after the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the sck pins will result in data for the content of the sector protection register being output on the so pin. the first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sec- tor 1 and the last byte (byte 8) corresponds to sector seven. once the last byte of the sector protection register has been clocked out, any additional clock pulses will result in undefined data being output on the so pin. the cs must be deasserted to terminate the read sector pro- tection register operation and put the output into a high-impedance state. table 9-6. read sector protection register command note: xx = dummy byte figure 9-4. read sector protection register 9.1.4 various aspects about the sector protection register the sector protection register is subject to a limit of 10,000 erase/program cycles. users are encouraged to carefully evaluate the number of times the sector protection register will be modified during the course of the applications? life cycle. if the application requires that the sec- tor protection register be modified more than the specified limit of 10,000 cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the sector protection register is reprogrammed), then the application will need to limit this practice. instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. command byte 1 byte 2 byte 3 byte 4 program sector protection register 3dh 2ah 7fh fch data byte n opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 data byte n + 1 data byte n + 7 cs each transition represents 8 bits si command byte 1 byte 2 byte 3 byte 4 read sector protection register 32h xxh xxh xxh opcode x x x data byte n data byte n + 1 cs data byte n + 7 si so each transition represents 8 bits
17 3595t?dflash?8/2013 AT45DB041D 10. security features 10.1 sector lockdown the device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read only. this is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. once a sector is locked down, it can never be erased or pro- grammed, and it can never be unlocked. to issue the sector lockdown command, the c s pin must first be asserted as it would be for any other command. once the c s pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and 30h. after the last byte of the command sequence has been clocked in, then three address bytes specifying any address within the sec- tor to be locked down must be clocked into the device. after the last address bit has been clocked in, the c s pin must then be deasserted to initiate the internally self-timed lockdown sequence. the lockdown sequence should take place in a maximum time of t p , during which time the status register will indicate that the device is busy. if the device is powered-down before the comple- tion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. in this case, it is recommended that the user read the sector lockdown register to determine the status of the appropriate sector lockdown bits or bytes and reissue the sector lockdown com- mand if necessary. table 10-1. sector lockdown figure 10-1. sector lockdown command byte 1 byte 2 byte 3 byte 4 sector lockdown 3dh 2ah 7fh 30h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs address bytes address bytes address bytes each transition represents 8 bits si
18 3595t?dflash?8/2013 AT45DB041D 10.1.1 sector lockdown register sector lockdown register is a nonvolatile register that contains 16-bytes of data, as shown below: table 10-2. sector lockdown register 10.1.2 reading the sector lockdown register the sector lockdown register can be read to determine which sectors in the memory array are permanently locked down. to read the sector lockdown register, the c s pin must first be asserted. once the c s pin has been asserted, an opcode of 35h and three dummy bytes must be clocked into the device via the si pin. after the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the sector lockdown register will be clocked out on the so pin. the first byte corresponds to sector 0 (0a, 0b) the second byte corresponds to sector one and the las byte (byte 8) corresponds to sector seven. after the last byte of the sector lockdown register has been read, additional pulses on the sck pin will simply result in unde- fined data being output on the so pin. deasserting the cs pin will terminate the read sector lockdown register operation and put the so pin into a high-impedance state. table 10-4 details the values read from the sector lockdown register. figure 10-2. read sector lockdown register sector number 0 (0a, 0b) 1 to 7 locked see below ffh unlocked 00h table 10-3. sector 0 (0a, 0b) 0a 0b bit 3, 2 data value (page 0-7) (page 8-255) bit 7, 6 bit 5, 4 bit 1, 0 sectors 0a, 0b unlocked 00 00 00 00 00h sector 0a locked (page 0-7) 11 00 00 00 c0h sector 0b locked (page 8-255) 00 11 00 00 30h sectors 0a, 0b locked (page 0-255) 11 11 00 00 f0h table 10-4. sector lockdown register command byte 1 byte 2 byte 3 byte 4 read sector lockdown register 35h xxh xxh xxh note: xx = dummy byte opcode x x x data byte n data byte n + 1 cs data byte n + 7 si so each transition represents 8 bits
19 3595t?dflash?8/2013 AT45DB041D 10.2 security register the device contains a specialized security register that can be used for purposes such as unique device serialization or locked key storage. the register is comprised of a total of 128- bytes that is divided into two portions. the first 64-bytes (byte locations 0 through 63) of the security register are allocated as a one-time us er programmable space. once these 64 bytes have been programmed, they cannot be reprogrammed. the remaining 64-bytes of the register (byte locations 64 through 127) are factory programmed by adesto and will contain a unique value for each device. the factory programmed data is fixed and cannot be changed. 10.2.1 programming the security register the user programmable portion of the security register does not need to be erased before it is programmed. to program the security register, the c s pin must first be asserted and the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4-byte opcode sequence must start with 9bh and be followed by 00h, 00h, and 00h. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the security register must be clocked in. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the inter- nally self-timed program cycle. the programming of the security register should take place in a time of t p , during which time the status register will indicate that the device is busy. if the device is powered-down during the program cycle, then the contents of the 64-byte user programmable portion of the security register cannot be guaranteed. if the full 64-bytes of data is not clocked in before the c s pin is deasserted, then the values of the byte locations not clocked in cannot be guar anteed. for example, if only the first two bytes are clocked in instead of the complete 64-bytes, then the remaining 62-bytes of the user pro- grammable portion of the security register cannot be guaranteed. furthermore, if more than 64- bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for instance, if 65-bytes of data are clocked in, then the 65 th byte will be stored at byte location 0 of the security register. the user programmable portion of the security register can only be programmed one time. therefore, it is not possible to only program the first two bytes of the register and then pro- gram the remaining 62-bytes at a later time. the program security register command utilizes the internal sram buffer 1 for processing. therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. figure 10-3. program security register table 10-5. security register security register byte number 01 ????? 62 63 64 65 ????? 126 127 data type one-time user programmable factory programmed by adesto data byte n opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 data byte n + 1 data byte n + 63 cs each transition represents 8 bits si
20 3595t?dflash?8/2013 AT45DB041D 10.2.2 reading the security register the security register can be read by first asserting the c s pin and then clocking in an opcode of 77h followed by three dummy bytes. after the last don't care bit has been clocked in, the con- tent of the security register can be clocked out on the so pins. after the last byte of the security register has been read, additional pulses on the sck pin will simply result in undefined data being output on the so pins. deasserting the cs pin will terminate the read security register operation and put the so pins into a high-impedance state. figure 10-4. read security register 11. additional commands 11.1 main memory page to buffer transfer a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation for the dataflash standard page size (264-bytes), a 1-byte opcode, 53h for buffer 1 and 55h for buffer 2, must be clocked into the device, follo wed by three address bytes com- prised of four don?t care bits, 11 page address bits (pa10 - pa0), which specify the page in main memory that is to be transferred, and nine don?t care bits. to perform a main memory page to buffer transfer for the binary page size (256-bytes), the opcode 53h for buffer 1 or 55h for buffer 2, must be clocked into the device followed by three address bytes consisting of five don?t care bits, 11 page address bits (a18 - a8) which specify the page in the main memory that is to be transferred, and eight don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been completed. 11.2 main memory page to buffer compare a page of data in main memory can be compared to the data in buffer 1 or buffer 2. to initiate the operation for the dataflash standard page size, a 1-byte opcode, 60h for buffer 1 and 61h for buffer 2, must be clocked into the device, followed by three address bytes consisting of four don?t care bits, 11 page address bits (pa10 - pa0) that specify the page in the main mem- ory that is to be compared to the buffer, and 9 don?t care bits. to start a main memory page to buffer compare for a binary page size, the opcode 60h for buffer 1 or 61h for buffer 2, must be clocked into the device followed by three address bytes consisting of five don?t care bits, 11 page address bits (a18 - a8) that specify the page in the main memory that is to be compared to the buffer, and eight don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). on the low-to-high transition of the cs pin, the data bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. during this time (t comp ), the status register will indicate that the part is busy. opcode x x x data byte n data byte n + 1 cs data byte n + x each transition represents 8 bits si so
21 3595t?dflash?8/2013 AT45DB041D on completion of the compare operation, bit six of the status register is updated with the result of the compare. 11.3 auto page rewrite this mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. to start the rewrite operation for the dataflash standard page size (264-bytes), a 1-byte opcode, 58h for buffer 1 or 59h for buffer 2, must be clocked into the device, followed by three address bytes comprised of four don?t care bits, 11 page address bits (pa10-pa0) that specify the page in main memory to be rewritten and nine don?t care bits. to initiate an auto page rewrite for a binary page size (256-bytes), the opcode 58h for buffer 1 or 59h for buffer 2, must be clocked into the device followed by three address bytes consisting of five don?t care bits, 11 page address bits (a18 - a8) that specify the page in the main memory that is to be written and eight don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 25-1 ( page 45 ) is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 25-2 ( page 46 ) is recommended. each page within a sector must be updated/rewritten at least once within every 20,000 cumulative page erase/program operations in that sector. please contact adesto for availab ility of devices that are specified to exceed the 20k cycle cumulative limit. 11.4 status register read the status register can be used to determine the device?s ready/busy status, page size, a main memory page to buffer compare operation result, the sector protection status or the device density. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the c s pin must be asserted and the opcode of d7h must be loaded into the device. after the opcode is clocked in, the 1-byte status register will be clocked out on the output pin (so), starting with the next clock cycle. the data in the status register, starting with the msb (bit 7), will be clocked out on the so pin during the next eight clock cycles. after the one byte of the status register has been clocked out, the sequence will repeat itself (as long as c s remains low and sck is being toggled). the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit seven of the status register. if bit seven is a one, then the device is not busy and is ready to accept the next command. if bit seven is a zero, then the device is in a busy state. since the data in the status register is constantly updated, the user must toggle sck pin to check the ready/busy status. there are several operations that can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffe r to main memory page progr am, main memory page program through buffer, page erase, block erase, sector erase, chip erase and auto page rewrite.
22 3595t?dflash?8/2013 AT45DB041D the result of the most recent main memory page to buffer compare operation is indicated using bit six of the status register. if bit six is a zero, then the data in the main memory page matches the data in the buffer. if bit six is a one, then at least one bit of the data in the main memory page does not match the data in the buffer. bit one in the status register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-con- trolled method. a logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled. bit zero in the status register indicates whether the page size of the main memory array is con- figured for ?power of 2? binary page size (256-bytes) or the dataflash standard page size (264- bytes). if bit zero is a on e, then the page size is set to 256-bytes. if bit zero is a zero, then the page size is set to 264-bytes. the device density is indicated using bits five, four, three, and two of the status register. for the AT45DB041D, the four bits are 0111 the decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of dataflash devices. the device density is not the same as the density code indicated in the jedec device id information. the device density is provided only for backward compatibility. 12. deep power-down after initial power-up, the device will default in standby mode. the deep power-down command allows the device to enter into the lowest power consumption mode. to enter the deep power- down mode, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of b9h command must be clocked in via input pin (si). after the last bit of the command has been clocked in, the c s pin must be de-asserted to initiate the deep power-down operation. after the c s pin is de-asserted, the will device enter the deep power-down mode within the maximum t edpd time. once the device has entered the deep power-down mode, all instructions are ignored except for the resume from deep power-down command. table 12-1. deep power-down figure 12-1. deep power-down table 11-1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/ busy comp 0 1 1 1 protect page size command opcode deep power-down b9h opcode cs each transition represents 8 bits si
23 3595t?dflash?8/2013 AT45DB041D 12.1 resume from deep power-down the resume from deep power-down command takes the device out of the deep power-down mode and returns it to the normal standby mode. to resume from deep power-down mode, the cs pin must first be asserted and an opcode of abh command must be clocked in via input pin (si). after the last bit of the command has been clocked in, the c s pin must be de-asserted to terminate the deep power-down mode. after the cs pin is de-asserted, the device will return to the normal standby mode within the maximum t rdpd time. the c s pin must remain high during the t rdpd time before the device can receive any commands. after resuming form deep power- down, the device will return to the normal standby mode. table 12-2. resume from deep power-down figure 12-2. resume from deep power-down 13. ?power of 2? binary page size option ?power of 2? binary page size configuration register is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size (256- bytes) or the dataflash standard page size (264-bytes). the ?power of 2? page size is a one- time programmable configuration register and once the device is configured for ?power of 2? page size, it cannot be reconfigured again. the devices are initially shipped with the page size set to 264-bytes. the user has the option of ordering binary page size (256-bytes) devices from the factory. for details, please refer to section 26. ?ordering information? on page 47 . for the binary ?power of 2? page size to become effective, the following steps must be followed: 1. program the one-time programmable configuration resister using opcode sequence 3dh, 2ah, 80h and a6h (please see section 13.1 ). 2. power cycle the device (i.e. power down and power up again). 3. the page for the binary page size can now be programmed. if the above steps are not followed to set the page size prior to page programming, incorrect data during a read operation may be encountered. command opcode resume from deep power-down abh opcode cs each transition represents 8 bits si
24 3595t?dflash?8/2013 AT45DB041D 13.1 programming the configuration register to program the configuration register for ?power of 2? binary page size, the cs pin must first be asserted as it would be with any other command. once the c s pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4-byte opcode sequence must start with 3dh and be followed by 2ah, 80h, and a6h. after the last bit of the opcode sequence has been clocked in, the c s pin must be deasserted to initiate the internally self-timed program cycle. the pr ogramming of the configuration register should take place in a time of t p , during which time the status register will indicate that the device is busy. the device must be power-cycled after the completion of the program cycle to set the ?power of 2? page size. if the device is powered-down before the completion of the program cycle, then setting the configuration register cannot be guaranteed. however, the user should check bit zero of the status register to see whether the page size was configured for binary page size. if not, the command can be re-issued again. table 13-1. programming the configuration register figure 13-1. erase sector protection register 14. manufacturer and device id read identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. to read the identification information, the c s pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin out- putting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be the extended device information string length, which will be 00h indicating that no extended device information follows. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the c s pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. command byte 1 byte 2 byte 3 byte 4 power of two page size 3dh 2ah 80h a6h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
25 3595t?dflash?8/2013 AT45DB041D 14.1 manufacturer and device id information note: based on jedec publication 106 (jep106), manufacturer id data can be comprised of any number of bytes. some manufac- turers may have manufacturer id codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7fh. a system should detect code 7fh as a ?continuation code? and continue to read manufacturer id bytes. the first non- 7fh byte would signify the last byte of manufacturer id data. for adesto (and some other manufacturers), the manufacturer id data is comprised of only one byte. 14.1.1 byte 1 ? manufacturer id hex value jedec assigned code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1fh 0 0 0 1 1 1 1 1 manufacturer id 1fh = adesto 14.1.2 byte 2 ? device id (part 1) hex value family code density code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 family code 001 = dataflash 24h 0 0 1 0 0 1 0 0 density code 00100 = 4-mbit 14.1.3 byte 3 ? device id (part 2) hex value mlc code product version code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mlc code 000 = 1-bit/cell technology 00h 0 0 0 0 0 0 0 0 product version 00000 = initial version 14.1.4 byte 4 ? extended device information string length hex value byte count bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h 0 0 0 0 0 0 0 0 byte count 00h = 0 bytes of information 9fh manufacturer id byte n device id byte 1 device id byte 2 this information would only be output if the extended device information string length value was something other than 00h. extended device information string length extended device information byte x extended device information byte x + 1 cs 1fh 24h 00h 00h data data si so opcode each transition represents 8 bits
26 3595t?dflash?8/2013 AT45DB041D 14.2 operation mode summary the commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. group a commands consist of: 1. main memory page read 2. continuous array read 3. read sector protection register 4. read sector lockdown register 5. read security register group b commands consist of: 1. page erase 2. block erase 3. sector erase 4. chip erase 5. main memory page to buffer 1 (or 2) transfer 6. main memory page to buffer 1 (or 2) compare 7. buffer 1 (or 2) to main memory page program with built-in erase 8. buffer 1 (or 2) to main memory page program without built-in erase 9. main memory page program through buffer 1 (or 2) 10. auto page rewrite group c commands consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read 4. manufacturer and device id read group d commands consist of: 1. erase sector protection register 2. program sector protection register 3. sector lockdown 4. program security register if a group a command is in progress (not fully completed), then another command in group a, b, c, or d should not be started. however, during the internally self-timed portion of group b commands, any command in group c can be executed. the group b commands using buffer 1 should use group c commands using buffer 2 and vice versa. finally, during the internally self- timed portion of a group d command, only the status register read command should be executed.
27 3595t?dflash?8/2013 AT45DB041D 15. command tables table 15-1. read commands command opcode main memory page read d2h continuous array read (legacy command) e8h continuous array read (low frequency) 03h continuous array read (high frequency) 0bh buffer 1 read (low frequency) d1h buffer 2 read (low frequency) d3h buffer 1 read d4h buffer 2 read d6h table 15-2. program and erase commands command opcode buffer 1 write 84h buffer 2 write 87h buffer 1 to main memory page program with built-in erase 83h buffer 2 to main memory page program with built-in erase 86h buffer 1 to main memory page program without built-in erase 88h buffer 2 to main memory page program without built-in erase 89h page erase 81h block erase 50h sector erase 7ch chip erase c7h, 94h, 80h, 9ah main memory page program through buffer 1 82h main memory page program through buffer 2 85h table 15-3. protection and security commands command opcode enable sector protection 3dh + 2ah + 7fh + a9h disable sector protection 3dh + 2ah + 7fh + 9ah erase sector protection register 3dh + 2ah + 7fh + cfh program sector protection register 3dh + 2ah + 7fh + fch read sector protection register 32h sector lockdown 3dh + 2ah + 7fh + 30h
28 3595t?dflash?8/2013 AT45DB041D note: 1. these legacy commands are not recommended for new designs. read sector lockdown register 35h program security register 9bh + 00h + 00h + 00h read security register 77h table 15-4. additional commands command opcode main memory page to buffer 1 transfer 53h main memory page to buffer 2 transfer 55h main memory page to buffer 1 compare 60h main memory page to buffer 2 compare 61h auto page rewrite through buffer 1 58h auto page rewrite through buffer 2 59h deep power-down b9h resume from deep power-down abh status register read d7h manufacturer and device id read 9fh table 15-5. legacy commands (1) command opcode buffer 1 read 54h buffer 2 read 56h main memory page read 52h continuous array read 68h status register read 57h table 15-3. protection and security commands command opcode
29 3595t?dflash?8/2013 AT45DB041D notes: x = don?t care table 15-6. detailed bit-level addressing sequence for binary page size (256-bytes) page size = 256-bytes address byte address byte address byte additional don?t care bytes opcode opcode reserved reserved reserved reserved reserved a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 03h 0 0 0 0 0 0 1 1 x x x x xaa a aaaaaaa a aaaaaaa a n/a 0bh 0 0 0 0 1 0 1 1 x x x x xaa a aaaaaaa a aaaaaaa a 1 50h 0101000 0 xxxxxaaaaaaaaxx x xxxxxxx x n/a 53h 0101001 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 55h 0101010 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 58h 0101100 0 xxxxxaaaaaaaaaaaxxxxxxx x n/a 59h 0101100 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 60h 0110000 0 xxxxxaaaaaaaaaaaxxxxxxx x n/a 61h 0110000 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 77h 0111011 1 xxxxxxx x xxxxxxx x xxxxxxx x n/a 7ch 0111110 0 xxxxxaaaxxxxxxx x xxxxxxx x n/a 81h 1000000 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 82h 1 0 0 0 0 0 1 0 x x x x xaa a aaaaaaa a aaaaaaa a n/a 83h 1000001 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 84h 1000010 0 xxxxxxx x xxxxxxx xaaaaaaa a n/a 85h 1 0 0 0 0 1 0 1 x x x x xaa a aaaaaaa a aaaaaaa a n/a 86h 1000011 0 xxxxxaaaaaaaaaaaxxxxxxx x n/a 87h 1000011 1 xxxxxxx x xxxxxxx xaaaaaaa a n/a 88h 1000100 0 xxxxxaaaaaaaaaaaxxxxxxx x n/a 89h 1000100 1 xxxxxaaaaaaaaaaaxxxxxxx x n/a 9fh 1 0 0 1 1 1 1 1 n/a n/a n/a n/a b9h 1 0 1 1 1 0 0 1 n/a n/a n/a n/a abh 1 0 1 0 1 0 1 1 n/a n/a n/a n/a d1h 1101000 1 xxxxxxx x xxxxxxx xaaaaaaa a n/a d2h 1 1 0 1 0 0 1 0 x x x x xaa a aaaaaaa a aaaaaaa a 4 d3h 1101001 1 xxxxxxx x xxxxxxx xaaaaaaa a n/a d4h 1101010 0 xxxxxxx x xxxxxxx xaaaaaaa a 1 d6h 1101011 0 xxxxxxx x xxxxxxx xaaaaaaa a 1 d7h 1 1 0 1 0 1 1 1 n/a n/a n/a n/a e8h 1 1 1 0 1 0 0 0 x x x x xaa a aaaaaaa a aaaaaaa a 4
30 3595t?dflash?8/2013 AT45DB041D notes: p = page address bit b = byte/buffer address bit x = don?t care table 15-7. detailed bit-level addressing sequence for standard dataflash page size (264-bytes) page size = 264-bytes address byte address byte address byte additional don?t care bytes opcode opcode reserved reserved reserved reserved pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 03h 0000001 1 xxxxpppppppppppbb bbbbbb b n/a 0bh 0000101 1 xxxxpppppppppppbb bbbbbb b 1 50h 0101000 0 xxxxppppppppxxx x xxxxxxx x n/a 53h 0101001 1 xxxxpppppppppppx xxxxxxx x n/a 55h 0101010 1 xxxxpppppppppppx xxxxxxx x n/a 58h 0101100 0 xxxxpppppppppppx xxxxxxx x n/a 59h 0101100 1 xxxxpppppppppppx xxxxxxx x n/a 60h 0110000 0 xxxxpppppppppppx xxxxxxx x n/a 61h 0110000 1 xxxxpppppppppppx xxxxxxx x n/a 77h 0111011 1 xxxxxxx x xxxxxxx x xxxxxxx x n/a 7ch 0111110 0 xxxxpppx xxxxxxx x xxxxxxx x n/a 81h 1000000 1 xxxxpppppppppppx xxxxxxx x n/a 82h 1000001 0 xxxxpppppppppppbb bbbbbb b n/a 83h 1000001 1 xxxxpppppppppppx xxxxxxx x n/a 84h 1000010 0 xxxxxxx x xxxxxxxbb bbbbbb b n/a 85h 1000010 1 xxxxpppppppppppbb bbbbbb b n/a 86h 1000011 0 xxxxpppppppppppx xxxxxxx x n/a 87h 1000011 1 xxxxxxx x xxxxxxxbb bbbbbb b n/a 88h 1000100 0 xxxxpppppppppppx xxxxxxx x n/a 89h 1000100 1 xxxxpppppppppppx xxxxxxx x n/a 9fh 1001111 1 n/a n/a n/a n/a b9h 1011100 1 n/a n/a n/a n/a abh 1010101 1 n/a n/a n/a n/a d1h 1101000 1 xxxxxxx x xxxxxxxbb bbbbbb b n/a d2h 1101001 0 xxxxpppppppppppbb bbbbbb b 4 d3h 1101000 1 xxxxxxx x xxxxxxxbb bbbbbb b n/a d4h 1101010 0 xxxxxxx x xxxxxxxbb bbbbbb b 1 d6h 1101011 0 xxxxxxx x xxxxxxxbb bbbbbb b 1 d7h 1101011 1 n/a n/a n/a n/a e8h 1110100 0 xxxxpppppppppppbb bbbbbb b 4
31 3595t?dflash?8/2013 AT45DB041D 16. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to mode 3. in addition, the output pin (so) will be in a high impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruction. the mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. 16.1 initial power-up/reset timing restrictions at power up, the device must not be selected until the supply voltage reaches the v cc (min.) and further delay of t vcsl . during power-up, the internal power-on reset circuitry keeps the device in reset mode until the v cc rises above the power-on reset threshold value (v por ). at this time, all operations are disabled and the device does no t respond to any commands. after power up is applied and the v cc is at the minimum operating voltage v cc (min.), the t vcsl delay is required before the device can be selected in order to perform a read operation. similarly, the t puw delay is required after the v cc rises above the power-on reset threshold value (v por ) before the device can perform a write (program or erase) operation. after initial power-up, the device will default in standby mode. table 16-1. initial power-up/reset timing restrictions 17. system considerations the rapids serial interface is controlled by the clock sck, serial input si and chip select c s pins. these signals must rise and fall monotonically and be free from noise. excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. the pc board traces must be kept to a minimum distance or appropriately termi- nated to ensure proper operation. if necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, volt age regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capability. like all flash memories, the peak current for dataflash occur during the programming and erase operation. the regulator needs to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. symbol parameter min typ max units t vcsl v cc (min.) to chip select low 70 s t puw power-up device delay before write allowed 20 ms v por power-on reset voltage 1.5 2.5 v
32 3595t?dflash?8/2013 AT45DB041D 18. electrical specifications table 18-1. absolute maximum ratings* temperature under bias ................................ -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. the "absolute maximum rat- ings" are stress ratings only and functional operation of the device at these or any other con- ditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the "absolute maximum ratings" are intended to accommo- date short duration undershoot/overshoot condi- tions and does not imply or guarantee functional device operation at these levels for any extended period of time. storage temperature..................................... -65 ? c to +150 ? c all input voltages (except v cc but including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v table 18-2. dc and ac operating range AT45DB041D (2.5v version) AT45DB041D operating temperature (case) ind. -40 ? c to 85 ? c -40 ? c to 85 ? c v cc power supply 2.5v to 3.6v 2.7v to 3.6v
33 3595t?dflash?8/2013 AT45DB041D notes: 1. i cc1 during a buffer read is 20ma maximum @ 20mhz. 2. all inputs (si, sck, cs#, wp#, and reset#) are guaranteed by design to be 5-volt tolerant. table 18-3. dc characteristics symbol parameter condition min typ max units i dp deep power-down current cs, reset, wp = v ih , all inputs at cmos levels 15 25 a i sb standby current cs, reset, wp = v ih , all inputs at cmos levels 25 50 a i cc1 (1) active current, read operation f = 20mhz; i out = 0ma; v cc = 3.6v 710ma f = 33mhz; i out = 0ma; v cc = 3.6v 812ma f = 50mhz; i out = 0ma; v cc = 3.6v 10 14 ma f = 66mhz; i out = 0ma; v cc = 3.6v 11 15 ma i cc2 active current, program/erase operation v cc = 3.6v 12 17 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 av cc - 0.2v v
34 3595t?dflash?8/2013 AT45DB041D table 18-4. ac characteristics ? rapids/serial interface symbol parameter AT45DB041D (2.5v version) AT45DB041D min typ max min typ max units f sck sck frequency 50 66 mhz f car1 sck frequency for continuous array read 50 66 mhz f car2 sck frequency for continuous array read (low frequency) 33 33 mhz t wh sck high time 6.8 6.8 ns t wl sck low time 6.8 6.8 ns t sckr (1) sck rise time, peak-to-peak (slew rate) 0.1 0.1 v/ns t sckf (1) sck fall time, peak-to-peak (slew rate) 0.1 0.1 v/ns t cs minimum cs high time 50 50 ns t css cs setup time 5 5 ns t csh cs hold time 5 5 ns t su data in setup time 2 2 ns t h data in hold time 3 3 ns t ho output hold time 0 0 ns t dis output disable time 27 35 27 35 ns t v output valid 8 6 ns t wpe wp low to protection enabled 1 1 s t wpd wp high to protection disabled 1 1 s t edpd cs high to deep power-down mode 3 3 s t rdpd cs high to standby mode 35 35 s t xfr page to buffer transfer time 200 200 s t comp page to buffer compare time 200 200 s t ep page erase and programming time (256/264 bytes) 14 35 14 35 ms t p page programming time (256-/264-bytes) 2 4 2 4 ms t pe page erase time (256-/264-bytes) 13 32 13 32 ms t be block erase time (2,048-/2,112-bytes) 30 75 30 75 ms t se sector erase time (65,536-/67,584-bytes) 0.7 1.3 0.7 1.3 s t ce chip erase time 5 12 5 12 s t rst reset pulse width 10 10 s t rec reset recovery time 1 1 s
35 3595t?dflash?8/2013 AT45DB041D 19. input test waveforms and measurement levels t r , t f < 2ns (10% to 90%) 20. output test load 21. ac waveforms six different timing waveforms are shown on page 36 . waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and waveform 2 shows the sck signal being high when c s makes a high-to-low transition. in both cases, output so becomes valid while the sck signal is still low (sck low time is specified as t wl ). timing waveforms 1 and 2 conform to rapids serial interface but for frequencies up to 66mhz. waveforms 1 and 2 are compatible with spi mode 0 and spi mode 3, respectively. waveform 3 and waveform 4 illustrate general timing diagram for rapids serial interface. these are similar to waveform 1 and waveform 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (max- imum frequency = 66mhz) of the rapids serial case. ac dri v i n g le v els ac measureme n t le v el 0.45 v 1.5 v 2.4 v device under test 30 pf
36 3595t?dflash?8/2013 AT45DB041D 21.1 waveform 1 ? spi mode 0 compatible (for frequencies up to 66mhz) 21.2 waveform 2 ? spi mode 3 compatible (for frequencies up to 66mhz) 21.3 waveform 3 ? rapids mode 0 (f max = 66mhz) 21.4 waveform 4 ? rapids mode 3 (f max = 66mhz) cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si
37 3595t?dflash?8/2013 AT45DB041D 21.5 utilizing the rapids function to take advantage of the rapids function's abilit y to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. the dataflash is designed to always clock its data out on the falling edge of the sck signal and clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the dataflash is clocking data out on the falling edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host controller should clock its data out on the rising edge of sck in order to give the dataflash a full clock cycle to latch the incoming data in on the next rising edge of sck. figure 21-1. rapids mode sck mosi miso 1 234567 81 234567 8 mosi = master out, slave in miso = master in, slave out the master is the host controller and the slave is the dataflash the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck. the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck. a. master clocks out first bit of byte-mosi on the rising edge of sck. b. slave clocks in first bit of byte-mosi on the next rising edge of sck. c. master clocks out second bit of byte-mosi on the same rising edge of sck. d. last bit of byte-mosi is clocked out from the master. e. last bit of byte-mosi is clocked into the slave. f. slave clocks out first bit of byte-so. g. master clocks in first bit of byte-so. h. slave clocks out second bit of byte-so. i. master clocks in last bit of byte-so. a b cd e f g 1 h byte-mosi msb lsb byte-so msb lsb slave cs i
38 3595t?dflash?8/2013 AT45DB041D 21.6 reset timing note: the cs signal should be in the high state before the reset signal is deasserted. 21.7 command sequence for read/write operations for page size 256-bytes (except status register read, manufacturer and device id read) 21.8 command sequence for read/write operations for page size 264-bytes (except status register read, manufacturer and device id read) cs sck reset so (output) high impedance high impedance si (input) t rst t rec t css si (input) cmd 8 bits 8 bits 8 bits page address (a18 - a8) x x x x x x x x x x x x x x x x lsb x x x x x x x x byte/buffer address (a7 - a0/bfa7 - bfa0) msb 5 don?t care bits page address (pa10 - pa0) byte/buffer address (ba8 - ba0/bfa8 - bfa0) si (input) cmd 8 bits 8 bits 8 bits x x x x x x x x x x x x lsb x x x x x x x x msb 4 don?t care bits x x x x
39 3595t?dflash?8/2013 AT45DB041D 22. write operations the following block diagram and waveforms illustrate the various write sequences available. 22.1 buffer write 22.2 buffer to main memory page program (data from buffer programmed into flash page) flash memory array page (256-/264-bytes) buffer 1 (256-/264-bytes) i/o interface si buffer 1 to main memory page program buffer 1 write buffer 2 (256-/264-bytes) buffer 2 to main memory page program buffer 2 write si (input) cmd completes writing into selected buffer cs x xx, bfa8 bfa7-0 n n+1 last byte binary page size 16 don't care + bfa7-bfa0 si (input) cmd pa10-7 pa6-0, x cs starts self-timed erase/program operation xxxx xx each transition represents 8 bits n = 1st byte read n+1 = 2nd byte read binary page size a18-a8 + 8 don't care bits
40 3595t?dflash?8/2013 AT45DB041D 23. read operations the following block diagram and waveforms illustrate the various read sequences available. 23.1 main memory page read 23.2 main memory page to buffer transfer (data from flash page read into buffer) flash memory array page (256-/264-bytes) buffer 2 (256-/264-bytes) buffer 1 (256-/264-bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so si (input) cmd pa10-7 pa6-0, ba8 x cs n n+1 so (output) ba7-0 4 dummy bytes x address for binary page size a18-a16 a15-a8 a7-a0 starts reading page data into buffer si (input) cmd pa10-7 pa6-0, x cs so (output) xxxx xxxx binary page size a18-a8 + 8 don't care bits
41 3595t?dflash?8/2013 AT45DB041D 23.3 buffer read 24. detailed bit-level read waveform ? rapids serial interface mode 0/mode 3 24.1 continuous array read (legacy opcode e8h) 24.2 continuous array read (opcode 0bh) cmd cs n n+1 x x x..x, bfa8 bfa7- 0 binary page size 16 don't care + bfa7-bfa0 each transition represents 8 bits si (input) so (output) no dummy byte (opcodes d1h and d3h) 1 dummy byte (opcodes d4h and d6h) sck cs si so msb msb 23 1 0 11101000 67 5 41011 9 812 636667 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits 32 don't care bits data byte 1 high-impedance bit 2047/2111 of page n bit 0 of page n+1 sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 812 394243 41 40 38 33 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits a18 - a0 don't care data byte 1 high-impedance 36 37 35 x x
42 3595t?dflash?8/2013 AT45DB041D 24.3 continuous array read (low frequency: opcode 03h) 24.4 main memory page read (opcode: d2h) 24.5 buffer read (opcode d4h or d6h) sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa aa msb msb dddddddd d d address bits a18-a0 data byte 1 high-impedance sck cs si so msb msb 23 1 0 11010010 67 5 41011 9 812 636667 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits 32 don't care bits data byte 1 high-impedance sck cs si so msb msb 23 1 0 11010100 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode xxxx aaa xx msb xxxxxxxx msb msb dddddddd d d address bits binary page size = 16 don't care + bfa7-bfa0 standard dataflash page size = 15 don't care + bfa8-bfa0 don't care data byte 1 high-impedance
43 3595t?dflash?8/2013 AT45DB041D 24.6 buffer read (low frequency: opcode d1h or d3h) 24.7 read sector protection register (opcode 32h) 24.8 read sector lockdown register (opcode 35h) sck cs si so msb msb 23 1 0 11010001 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx aaa xx msb msb dddddddd d d data byte 1 high-impedance address bits binary page size = 16 don't care + bfa7-bfa0 standard dataflash page size = 15 don't care + bfa8-bfa0 sck cs si so msb msb 23 1 0 00110010 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00110101 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance
44 3595t?dflash?8/2013 AT45DB041D 24.9 read security register (opcode 77h) 24.10 status register read (opcode d7h) 24.11 manufacturer and device read (opcode 9fh) sck cs si so msb msb 23 1 0 01110111 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance sck cs si so msb 23 1 0 11010111 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb dddddd dd d d msb dddddd d d status register data status register data high-impedance sck cs si so 6 0 9fh 8 7 38 opcode 1fh device id byte 1 device id byte 2 00h high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
45 3595t?dflash?8/2013 AT45DB041D 25. auto page rewrite flowchart figure 25-1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start mai n memory page program through buffer ( 8 2h, 8 5h) e n d pro v ide address and data buffer w rite ( 8 4h, 8 7h) buffer to mai n memory page program ( 8 3h, 8 6h)
46 3595t?dflash?8/2013 AT45DB041D figure 25-2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash sector must be updated/rewritten at least once within every 10,000 cumulative page erase and program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using adesto?s serial dataflash?) for more details. start mai n memory page to buffer tra n sfer (53h, 55h) i n creme n t page address poi n ter (2) auto page re w rite (2) (5 8 h, 59h) e n d pro v ide address of page to modify if planning to modify m u ltiple b ytes c u rrently stored w ithin a page of the flash array mai n memory page program through buffer ( 8 2h, 8 5h) buffer w rite ( 8 4h, 8 7h) buffer to mai n memory page program ( 8 3h, 8 6h)
47 3595t?dflash?8/2013 AT45DB041D 26. ordering information 26.1 ordering code detail notes: 1. the shipping carrier option is not marked on the devices. 2. standard parts are shipped with the page size set to 264-bytes. the user is able to configure these parts to a 256-byte page size if desired. 3. parts ordered with suffix sl954 are shipped in bulk with the page size set to 256-bytes. parts will have a 954 or sl954 marked on them. 4. parts ordered with suffix sl955 are shipped in tape and reel with the page size set to 256 bytes. parts will have a 954 or sl954 marked on them. at4 5d 0 4 ssu 1d? b designator product family device density 4 = 4-megabit interface 1 = serial package option m = 8-pad, 6 x 5 x 1mm mlf (vdfn) ss = 8-lead, 0.150" wide soic s = 8-lead, 0.209" wide soic device grade u = matte sn lead finish, industrial temperature range (-40c to +85c) device revision 26.2 green package options (pb/halide-free/rohs compliant) ordering code (1)(2) package lead finish operating voltage f sck (mhz) operation range AT45DB041D-mu AT45DB041D-mu-sl954 (3) AT45DB041D-mu-sl955 (4) 8m1-a matte sn 2.7v to 3.6v 66 industrial (-40c to +85c) AT45DB041D-ssu AT45DB041D-ssu-sl954 (3) AT45DB041D-ssu-sl955 (4) 8s1 AT45DB041D-su AT45DB041D-su-sl954 (3) AT45DB041D-su-sl955 (4) 8s2 AT45DB041D-mu-2.5 8m1-a matte sn 2.5v to 3.6v 50 AT45DB041D-ssu-2.5 8s1 AT45DB041D-su-2.5 8s2 package type 8m1-a 8-pad, 6 x 5 x 1.00mm body, very thin dual flat package no lead mlf ? (vdfn) 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.209? wide, plastic gull wing small outline package (eiaj soic)
48 3595t?dflash?8/2013 AT45DB041D 27. packaging information 27.1 8m1-a ? mlf (vdfn) title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8m1-a, 8-pad, 6 x 5 x 1.00mm body, thermally enhanced plastic very thin dual flat no lead package (vdfn) d 8m1-a ybr common dimensions (unit of measure = mm) symbol min nom max note a ? 0.85 1.00 a1 ? ? 0.05 a2 0.65 typ a3 0.20 typ b 0.35 0.40 0.48 d 5.90 6.00 6.10 d1 5.70 5.75 5.80 d2 3.20 3.40 3.60 e 4.90 5.00 5.10 e1 4.70 4.75 4.80 e2 3.80 4.00 4.20 e 1.27 l 0.50 0.60 0.75 ? ? 12 o k 0.25 ? ? pin 1 id top view pin #1 notch (0.20 r) bottom view d2 e2 l b d1 d e1 e e a3 a2 a1 a 0.08 c 0 side view 0 k 0.45 8/28/08
49 3595t?dflash?8/2013 AT45DB041D 27.2 8s1 ? jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: contact@adestotech.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
50 3595t?dflash?8/2013 AT45DB041D 27.3 8s2 ? eiaj soic title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8s2 stn f 8s2, 8-lead, 0.208? body, plastic small outline package (eiaj) 4/15/08 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. determines the true geometric position. 4. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 4 c 0.15 0.35 4 d 5.13 5.35 e1 5.18 5.40 2 e 7.70 8.26 l 0.51 0.85 q 0 8 e 1.27 bsc 3 q q 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w package drawing contact: contact@adestotech.com
51 3595t?dflash?8/2013 AT45DB041D 28. revision history revision level ? revision date history a ? october 2005 initial release b ? march 2006 added ?preliminary?. added text, in ?programming the configuration register?, to indicate that power cycling is required to switch to ?power of 2? page size after the opcode enable has been executed. added ?legacy commands? table. c ? june 2006 corrected typographical errors. d ? july 2006 corrected typographical errors. e ? august 2006 added errata regarding chip erase. f ? november 2006 removed ?preliminary?. g ? february 2007 removed rdy/ busy pin references. h ? march 2007 changed page size description from 512 to 256 in table 15-6 . changed page size description from 528 to 264 in table 15-7 . added additional text for ?power of 2? binary page size option. i ? april 2007 removed ser/ byte statement from si and so pin descriptions in table 2-1 . changed the number of don?t care bits from 17 to 16 for sector 1-15 erase in section 7.6 . corrected the density code description from 16-mbit to 4-mbit in section 14.1.2 . changed a16 address bit for opcode 7ch from ?x? to ?a? in table 15-6 . chagned pa8 address bit for opcode 7ch from ?x? to ?p? in table 15-7 . j ? august 2007 changed t xfr and t comp values from 40 s to 200 s. changed t vcsl from 50 s to 70 s. changed t rdpd from 30 s to 35 s. k ? december 2007 changed note 1 on page 14 from ?0 through 15? to ?0 through 7?. l ? april 2008 the chip erase command is supported on devices with date code 0810 and later. added chip erase time. added part nuber ordering code details for suffixes sl954/955. added ordering code detail. m ? february 2009 changed t dis (typ and max) to 27ns and 35ns, respectively. n ? march 2009 changed deep power-down current values - increased typical value from 5 a to 15 a. - increased maximum value from 15 a to 25 a. o ? april 2009 updated absolute maximum ratings removed chip erase errata p ? sept 2009 pg50: replace package drawing as per the attached
52 3595t?dflash?8/2013 AT45DB041D 29. errata 29.1 no errata conditions q ? may 2010 changed t se (typ) 1.6 to 0.7 and (max) 5 to 1.3 changed t ce (typ) 6 to 5 changed ba0 to pa0 row 50h in table 15-7 on page 30 . changed from 10,000 to 20,000 cumulative page erase/program operations in section 11.3 . added the ?please contact adesto for availability of devices that are specified to exceed the 20k cycle cumulative limit? statement in section 11.3 . r ? november 2012 update adesto logos s - january 2013 correct sector sizes and 2 buffer diagrams t- august 2013 not recommended for new designs. use at45db041e.
corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2013 adesto technologies. all rights reserved. / rev.: 3595t?dflash?8/2013 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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